MC68HC08AZ60 Datasheet, PDF (284/452 Pages) Motorola, Inc – Advance Information

I/O Ports
Freescale Semiconductor, Inc.
ATD[7:0] — ADC Channels
PTB7/ATD7–PTB0/ATD0 are eight of the analog-to-digital converter
channels. The ADC channel select bits, CH[4:0], determine whether
the PTB7/ATD7–PTB0/ATD0 pins are ADC channels or
general-purpose I/O pins. If an ADC channel is selected and a read of
this corresponding bit in the port B data register occurs, the data will
be 0 if the data direction for this bit is programmed as an input.
Otherwise, the data will reflect the value in the data latch. (See
Analog-to-Digital Converter (ADC-15) on page 395). Data direction
register B (DDRB) does not affect the data direction of port B pins that
are being used by the ADC. However, the DDRB bits always
determine whether reading port B returns to the states of the latches
or logic 0.
Data Direction
Register B
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address: $0005
Bit 7
6
5
4
3
2
1
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
Write:
Reset: 0
0
0
0
0
0
0
Figure 6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7 shows the port B I/O logic.
MC68HC08AZ60 — Rev 1.0
284
I/O Ports
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6-ioports
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