MC68HC08AZ60 Datasheet, PDF (130/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
The K factor in the equations is derived from internal PLL parameters.
K_acq is the K factor when the PLL is configured in acquisition mode, and
K_trk is the K factor when the PLL is configured in tracking mode. (See
Acquisition and Tracking Modes on page 111).
t_acq
=


V-f--_{R--D-D-D--V-A-}


K-----_A^8---_C^---_Q^{-}
t_al
=


V-f--_{R--D-D--D-V-A-}


-K----_T^4--_R---_K-_
t_Lock = t_ACQ + t_AL
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See Manual
and Automatic PLL Bandwidth Modes on page 111). A certain
number of clock cycles, n_ACQ, is required to ascertain that the PLL is
within the tracking mode entry tolerance, ∆_TRK, before exiting acquisition
mode. A certain number of clock cycles, n_TRK, is required to ascertain
that the PLL is within the lock mode entry tolerance, ∆_Lock. Therefore, the
acquisition time, t_ACQ, is an integer multiple of n_ACQ/f_RDV, and the
acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_RDV. Also,
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
t_Lock as calculated above.
In manual mode, it is usually necessary to wait considerably longer than
t_Lock before selecting the PLL clock (see Base Clock Selector Circuit
on page 115), because the factors described in Parametric Influences
on Reaction Time on page 128, may slow the lock time considerably.
MC68HC08AZ60 — Rev 1.0
130
Clock Generator Module (CGM)
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