MC68HC08AZ60 Datasheet, PDF (193/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
SCI During Break Module Interrupts
SCI During Break Module Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module on page
135).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
I/O Signals
PTE0/SCTxD
(Transmit Data)
PTE1/SCRxD
(Receive Data)
21-sci
MOTOROLA
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
• PTE0/SCTxD — Transmit data
• PTE1/SCRxD — Receive data
The PTE0/SCTxD pin is the serial data output from the SCI transmitter.
The SCI shares the PTE0/SCTxD pin with port E. When the SCI is
enabled, the PTE0/SCTxD pin is an output regardless of the state of the
DDRE2 bit in data direction register E (DDRE).
The PTE1/SCRxD pin is the serial data input to the SCI receiver. The
SCI shares the PTE1/SCRxD pin with port E. When the SCI is enabled,
the PTE1/SCRxD pin is an input regardless of the state of the DDRE1
bit in data direction register E (DDRE).
MC68HC08AZ60 — Rev 1.0
Serial Communications Interface Module (SCI)
193
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