MC68HC08AZ60 Datasheet, PDF (118/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Analog Power Pin
(V_DDA)
NOTE:
V_DDA is a power pin used by the analog portions of the PLL. Connect the
V_DDA pin to the same voltage potential as the V_DD pin.
Route V_DDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
Oscillator Enable The SIMOSCEN signal enables the oscillator and PLL.
Signal (SIMOSCEN)
Crystal Output
Frequency Signal
(CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f_xclk) and comes directly from the crystal oscillator circuit.
Figure 3 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
CGM Base Clock
Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal is used to generate
the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice
the bus frequency. CGMOUT is software programmable to be either the
oscillator output, CGMXCLK, divided by two or the VCO clock,
CGMVCLK, divided by two.
CGM CPU Interrupt CGMINT is the CPU interrupt signal generated by the PLL lock detector.
(CGMINT)
MC68HC08AZ60 — Rev 1.0
118
Clock Generator Module (CGM)
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14-cgm
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