MC68HC08AZ60 Datasheet, PDF (287/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
I/O Ports
Port C
Data Direction
Register C
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer
for the corresponding port C pin; a logic 0 disables the output buffer.
Address: $0006
Bit 7
6
5
4
3
2
1
Read:
0
MCLKEN
Write:
R
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1
Reset: 0
0
0
0
0
0
0
R = Reserved
Figure 9. Data Direction Register C (DDRC)
Bit 0
DDRC0
0
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, DDRC2 has no effect. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[5:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 10 shows the port C I/O logic.
9-ioports
MOTOROLA
MC68HC08AZ60 — Rev 1.0
I/O Ports
287
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