MC68HC08AZ60 Datasheet, PDF (342/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
MSCAN Controller (MSCAN08)
The bit time is determined by the oscillator frequency, the baud rate
prescaler, and the number of time quanta (T_q) clock cycles per bit as
shown in Table 9).
Pres value
Bit time= _fMSCANCLK • number of Time Quanta
NOTE: The CBTR1 register can only be written if the SFTRES bit in the
MSCAN08 module control register is set.
MSCAN08
Receiver Flag
Register (CRFLG)
All bits of this register are read and clear only. A flag can be cleared by
writing a 1 to the corresponding bit position. A flag can be cleared only
when the condition which caused the setting is valid no more. Writing a
0 has no effect on the flag setting. Every flag has an associated interrupt
enable flag in the CRIER register. A hard or soft reset will clear the
register.
Address: $0504
Bit 7
6
5
4
3
2
1
Bit 0
Read:
WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 19. Receiver Flag Register (CRFLG)
WUPIF — Wakeup Interrupt Flag
If the MSCAN08 detects bus activity while in Sleep mode, it sets the
WUPIF flag. If not masked, a wake-up interrupt is pending while this
flag is set.
1 = MSCAN08 has detected activity on the bus and requested
wake-up.
0 = No wake-up interrupt has occurred.
MC68HC08AZ60 — Rev 1.0
342
MSCAN Controller (MSCAN08)
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38-mscan
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