MC68HC08AZ60 Datasheet, PDF (274/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Modulo Timer (TIM)
I/O Registers
The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH–TCNTL)
• TIM counter modulo registers (TMODH–TMODL)
TIM Status and
Control Register
The TIM status and control register:
• Enables TIM interrupt
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: $004B
Bit 7
6
5
4
3
2
1
Bit 0
Read: TOF
0
0
TOIE TSTOP
Write: 0
TRST
PS2
PS1
PS0
Reset: 0
0
1
0
0
0
0
0
= Unimplemented
Figure 3. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIM
overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
MC68HC08AZ60 — Rev 1.0
274
Modulo Timer (TIM)
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