MC68HC08AZ60 Datasheet, PDF (92/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Illegal Address
Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset.
Extra care should be exercised if code running in these parts is
eventually shrunk into a smaller ROM size. Code errors may result
in illegal addresses being accessed. Devices with smaller ROM
sizes may behave in a different manner in this instance. Is is the
user’s responsibility to check their code for illegal addresses.
Also note that some HC08 devices generate illegal address resets
with data fetches under certain circumstances. User’s should
always check relevant data books and always check their code for
illegal addresses.
Low-Voltage
Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V_DD voltage falls to the V_LVII voltage. The LVI bit in the SIM reset
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG-1 register are at logic zero. The RST
pin will be held low until the SIM counts 4096 CGMXCLK cycles after
V_DD rises above V_LVIR. Another sixty-four CGMXCLK cycles later, the
CPU is released from reset to allow the reset vector sequence to occur.
See Low-Voltage Inhibit (LVI) on page 159.
MC68HC08AZ60 — Rev 1.0
92
System Integration Module (SIM)
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