MC68HC08AZ60 Datasheet, PDF (124/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Table 3. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency,
f_VRS. (See Circuits on page 109, Programming the PLL on page
113, and PLL Control Register on page 119.) VRS7–VRS4 cannot
be written when the PLLON bit in the PLL control register (PCTL) is
set. See Special Programming Exceptions on page 115. A value of
$0 in the VCO range select bits disables the PLL and clears the BCS
bit in the PCTL. (See Base Clock Selector Circuit on page 115 and
Special Programming Exceptions on page 115 for more
information.) Reset initializes the bits to $6 to give a default range
multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
MC68HC08AZ60 — Rev 1.0
124
Clock Generator Module (CGM)
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