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MC68HC08AZ60 Datasheet, PDF (352/452 Pages) Motorola, Inc – Advance Information
Freescale Semiconductor, Inc.
MSCAN Controller (MSCAN08)
AC7–AC0 — Acceptance Code Bits
AC7–AC0 comprise a user-defined sequence of bits with which the
corresponding bits of the related identifier register (IDRn) of the
receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
NOTE: The CIDAR0–3 registers can be written only if the SFTRES bit in
CMCR0 is set
MSCAN08
Identifier Mask
Registers
(CIDMR0-3)
The identifier mask registers specify which of the corresponding bits in
the identifier acceptance register are relevant for acceptance filtering.
For standatd identifiers it is required to program thelast three bits
(AM2-AM0) in the mask register CIDMR1 to ‘don’t care’.
CIDMRO Address: $0514
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by Reset
CIDMR1 Address: $0515
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by Reset
CIDMR2 Address: $0516
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by Reset
CIDMR3 Address: $0517
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by Reset
Figure 27. Identifier Mask Registers (CIDMR0–CIDMR3)
MC68HC08AZ60 — Rev 1.0
352
MSCAN Controller (MSCAN08)
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