MC68HC08AZ60 Datasheet, PDF (399/452 Pages) Motorola, Inc – Advance Information

Accuracy and
Precision
Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC-15)
Interrupts
cleared. The COCO bit is set after the first conversion and will stay set
for the next several conversions until the next write of the ADC status
and control register or the next read of the ADC data register.
The conversion process is monotonic and has no missing codes. See
ADC Characteristics on page 413 for accuracy information.
Interrupts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit (ADC status control register, $0038) is at logic 0. If the
COCO bit is set, an interrupt is generated. The COCO bit is not used as
a conversion complete flag when interrupts are enabled.
Low-Power Modes
The following subsections describe the low-power modes.
Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the ADCH[4:0] bits in the ADC status
and control register before executing the WAIT instruction.
Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
5-adc-15
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Analog-to-Digital Converter (ADC-15)
399
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