MC68HC08AZ60 Datasheet, PDF (197/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
I/O Registers
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See Table 8). Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE: Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 8. Character Format Selection
Control Bits
M
PEN:PTY
0
0X
1
0X
0
10
0
11
1
10
1
11
Start
Bits
1
1
1
1
1
1
Character Format
Data
Bits
Parity
Stop
Bits
8
None
1
9
None
1
7
Even
1
7
Odd
1
8
Even
1
8
Odd
1
Character
Length
10 Bits
11 Bits
10 Bits
10 Bits
11 Bits
11 Bits
SCI Control
Register 2
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
25-sci
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Serial Communications Interface Module (SCI)
197
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