MC68HC08AZ60 Datasheet, PDF (91/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Reset and System Initialization
OSC1
PORRST
CGMXCLK
CGMOUT
RST
IAB
Computer
Operating
Properly (COP)
Reset
Illegal Opcode
Reset
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE
$FFFF
Figure 7. POR Recovery
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
CONFIG-1 register is at logic zero.
See Computer Operating Properly Module (COP) on page 153.
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the MOR register is logic zero, the SIM
treats the STOP instruction as an illegal opcode and causes an illegal
opcode reset.
9-sim
MOTOROLA
MC68HC08AZ60 — Rev 1.0
System Integration Module (SIM)
91
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