MC68HC08AZ60 Datasheet, PDF (87/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM Bus Clock Control and Generation
SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 3. This clock can come
from either an external oscillator or from the on-chip PLL. (See
Clock Generator Module (CGM) on page 105).
Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See Clock Generator Module (CGM) on page 105).
Clock Startup from
POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after 4096 CGMXCLK cycles. The
RST pin is driven low by the SIM during this entire period. The bus clocks
start upon completion of the timeout.
OSC1
CLOCK
SELECT
÷2
CGMVCLK
CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGM
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
Figure 3. CGM Clock Signals
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
5-sim
MOTOROLA
MC68HC08AZ60 — Rev 1.0
System Integration Module (SIM)
87
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