MC68HC08AZ60 Datasheet, PDF (300/452 Pages) Motorola, Inc – Advance Information

I/O Ports
Freescale Semiconductor, Inc.
Data Direction
Register G
Data direction register G determines whether each port G pin is an input
or an output. Writing a logic 1 to a DDRG bit enables the output buffer
for the corresponding port G pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$000E
Bit 7
6
5
4
3
2
1
0
0
0
0
0
DDRG2 DDRG1
R
R
R
R
R
0
0
0
0
0
0
0
R = Reserved
Figure 21. Data Direction Register G (DDRG)
Bit 0
DDRG0
0
DDRG[2:0] — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears
DDRG[2:0], configuring all port G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE: Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 22 shows the port G I/O logic.
READ DDRG ($000E)
WRITE DDRG ($000E)
RESET
WRITE PTG ($000A)
DDRGx
PTGx
PTGx
READ PTG ($000A)
Figure 22. Port G I/O Circuit
MC68HC08AZ60 — Rev 1.0
300
I/O Ports
For More Information On This Product,
Go to: www.freescale.com
22-ioports
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