MC68HC08AZ60 Datasheet, PDF (220/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Transmission
Format When
CPHA = 1
SCK CYCLE #
FOR REFERENCE
SCK CPOL = 0
SCK CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
SS TO SLAVE
CAPTURE STROBE
Figure 4 shows an SPI transmission in which CPHA (SPCR) is logic 1.
The figure should not be used as a replacement for data sheet
parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See Mode Fault Error on page 225). When CPHA = 1, the master
begins driving its MOSI pin on the first SPSCK edge. Therefore, the
slave uses the first SPSCK edge as a start transmission signal. The SS
pin can remain low between transmissions. This format may be
preferable in systems having only one master and only one slave driving
the MISO data line.
1
2
3
4
5
6
7
8
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
Figure 4. Transmission Format (CPHA = 1)
MC68HC08AZ60 — Rev 1.0
220
Serial Peripheral Interface Module (SPI)
For More Information On This Product,
Go to: www.freescale.com
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