MC68HC08AZ60 Datasheet, PDF (236/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR $0010)
• SPI status and control register (SPSCR $0011)
• SPI data register (SPDR $0012)
SPI Control
Register
The SPI control register:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
• Enables the SPI module
Address: $0010
Bit 7
6
5
4
3
2
1
Read:
SPRIE
Write:
R SPMSTR CPOL CPHA SPWOM SPE
Reset: 0
0
1
0
1
0
0
R = Reserved
Figure 11. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
MC68HC08AZ60 — Rev 1.0
236
Serial Peripheral Interface Module (SPI)
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