MC68HC08AZ60 Datasheet, PDF (251/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
Functional Description
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
PTEx/TCHx
PULSE
WIDTH
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 3. PWM Period and Pulse Width
OUTPUT
COMPARE
The value in the TIMB counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMB counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see TIMB Status and Control Register).
The value in the TIMB channel registers determines the pulse width of
the PWM output. The pulse width of an 8-bit PWM signal is variable in
256 increments. Writing $0080 (128) to the TIMB channel registers
produces a duty cycle of 128/256 or 50%.
Unbuffered PWM
Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in Pulse Width Modulation (PWM) on page 250. The pulses
are unbuffered because changing the pulse width requires writing the
new pulse width value over the value currently in the TIMB channel
registers.
An unsynchronized write to the TIMB channel registers to change a
pulse width value could cause incorrect operation for up to two PWM
periods. For example, writing a new value before the counter reaches
the old value but after the counter reaches the new value prevents any
compare during that PWM period. Also, using a TIMB overflow interrupt
routine to write a new, smaller pulse width value may cause the compare
to be missed. The TIMB may pass the new value before it is written to
the TIMB channel registers.
9-timb
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Timer Interface Module B (TIMB)
251
For More Information On This Product,
Go to: www.freescale.com