MC68HC08AZ60 Datasheet, PDF (161/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
Functional Description
LVISTOP, enables the LVI module during stop mode. This will ensure
when the STOP instruction is implemented, the LVI will continue to
monitor the voltage level on V_DD. LVIPWR, LVISTOP, and LVIRST are
in the MOR register. (See Mask Options on page 131).
Once an LVI reset occurs, the MCU remains in reset until V_DD rises
above a voltage, LVI_TRIPR. V_DD must be above LVI_TRIPR for only one
CPU cycle to bring the MCU out of reset. (See Forced Reset Operation
on page 162). The output of the comparator controls the state of the
LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V_DD
LOW V_DD
DETECTOR
LVIPWR
FROM MOR
CPU CLOCK
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
V_DD
DIGITAL FILTER
FROM MOR
LVIRST
ANLGTRIP
Stop Mode
Filter Bypass
LVISTOP
FROM MOR
LVIOUT
Figure 1. LVI Module Block Diagram
LVI RESET
3-lvi
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Low-Voltage Inhibit (LVI)
161
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