MC68HC08AZ60 Datasheet, PDF (162/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
Addr.
$FE0F
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
LVI Status Register (LVISR) LVIOUT
= Unimplemented
Figure 2. LVI I/O Register Summary
Polled LVI
Operation
In applications that can operate at V_DD levels below the LVI_TRIPF level,
software can monitor V_DD by polling the LVIOUT bit. In the mask option
register, the LVIPWR bit must be at logic 1 to enable the LVI module, and
the LVIRST bit must be at logic 0 to disable LVI resets.
Forced Reset
Operation
In applications that require V_DD to remain above the LVI_TRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when V_DD
falls to the LVI_TRIPF level and remains at or below that level for nine or
more consecutive CPU cycles. In the mask option register, the LVIPWR
and LVIRST bits must be at logic 1 to enable the LVI module and to
enable LVI resets.
False Reset
Protection
The V_DD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU,V_DD must
remain at or below the LVI_TRIPF level for nine or more consecutive CPU
cycles. V_DD must be above LVI_TRIPR for only one CPU cycle to bring the
MCU out of reset.
MC68HC08AZ60 — Rev 1.0
162
Low-Voltage Inhibit (LVI)
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