MC9S12HY64 Datasheet, PDF (99/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12HYPIMV1)
Table 2-38. DDRH Register Field Descriptions
Field
7-4
DDRH
Description
Port H data direction—
This register controls the data direction of pin 7-4.
If enabled the LCD segment output it will force the I/O state to be a input/output diabled.
3
DDRH
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 3.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the IIC is routing to PH and IIC is enabled, the IIC will determined the pin direction
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction
2
DDRH
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 2.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction
Else if ECLK is enabled, it will force the pin to output.
1
DDRH
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 1.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction.
0
DDRH
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 0.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the IIC is routing to PH and IIC is enabled, the IIC will determined the pin direction
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction t.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
99