MC9S12HY64 Datasheet, PDF (113/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12HYPIMV1)
Table 2-55. PIFT Register Field Descriptions
Field
Description
6-5
PIFT
Port T interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPST register. To clear this flag, write logic level 1 to the corresponding bit in the PIFT register. Writing
a 0 has no effect.¹
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
1 _{In order to enable the key wakup function, need to disable the LCD FP function first}
2.3.67 Port S Interrupt Enable Register (PIES)
Read: Anytime.
Address 0x028A
7
R
0
W
Reset
0
1 _{Read: Anytime.}
Write: Anytime.
6
5
4
3
2
0
0
0
PIES6
PIES5
0
0
0
0
0
Figure 2-65. Port S Interrupt Enable Register (PIES)
Access: User read/write¹
1
0
0
0
0
0
Field
6-5
PIES
Table 2-56. PIES Register Field Descriptions
Description
Port S interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port S.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
2.3.68 Port S Interrupt Flag Register (PIFS)
Address 0x028B
7
R
0
W
Reset
0
1 _{Read: Anytime.}
Write: Anytime.
6
5
4
3
2
0
0
0
PIFS6
PIFS5
0
0
0
0
0
Figure 2-66. Port S Interrupt Flag Register (PIFS)
Access: User read/write¹
1
0
0
0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
113