MC9S12HY64 Datasheet, PDF (127/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

2.3.87 Port V Slew Rate Register(SRRV)
Port Integration Module (S12HYPIMV1)
Address 0x029E
R
W
Reset
7
SRRV7
0
1 _{Read: Anytime.}
Write: Anytime.
6
SRRV6
5
SRRV5
4
SRRV4
3
SRRV3
2
SRRV2
0
0
0
0
0
Figure 2-85. Port V Polarity Select Register (SRRV)
Access: User read/write¹
1
0
SRRV1
SRRV0
0
0
Table 2-73. SRRV Register Field Descriptions
Field
Description
7-0
SRRV
Port V Slew Rate Register—Determine the slew rate on the pins¹
1 Enable the slew rate control and disables the digital input buffer²
0 Disable the slew rate control and enable the digital input buffer
1 _{When change SRRV from non-zero value to zero value or vice versa, It will need to wait about 300 nanoseconds delay before}
the slew rate control to be real function as setting. When enter STOP, to save the power, the slew rate control will be force to off
state. After wakeup from STOP, it will also need to wait about 300 nanoseconds before slew rate control to be function as setting.
2 _{When MC function is disabled and IIC/SPI/PWM async shutdown are routing to PV and enabled, the corresponding digital input}
buffer will be always enabled
2.3.88 PIM Reserved Registers
Address 0x029F
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-86. PIM Reserved Registers
2.4 Functional Description
Access: User read¹
1
0
0
0
0
0
2.4.1 General
Each pin except BKGD can act as general purpose I/O. In addition each pin can act as an output or input
of a peripheral module.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
127