MC9S12HY64 Datasheet, PDF (88/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12HYPIMV1)
Table 2-21. DDRS Register Field Descriptions (continued)
Field
3
DDRS
Description
Port S data direction—
This register controls the data direction of pin 3.This register configures pin as either input or output.
If CAN is enabled, it will force the pin as output.
2
DDRS
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S data direction—
This register controls the data direction of pin 2.This register configures pin as either input or output.
If CAN is enabled, it will force the pin as input.
1
DDRS
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S data direction—
This register controls the data direction of pin 1.This register configures pin as either input or output.
If SCI is enabled, it will force the pin as output
Else if PWM7 is routing to PS1 and use as PWM channel output, it will force pin as output. If use as PWM emergency
shut down, it will force pin as input.
0
DDRS
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S data direction—
This register controls the data direction of pin 0.This register configures pin as either input or output.
If SCI is enabled, it will force the pin as input
Else if PWM6 is routing to PS0 and PWM6 is enabled, it will force pin as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTS or PTIS registers, when changing the
DDRS register.
2.3.25 Port S Reduced Drive Register (RDRS)
Address 0x024B
R
W
Reset
7
RDRS7
0
1 _{Read: Anytime.}
Write: Anytime.
6
RDRS6
5
RDRS5
4
RDRS4
3
RDRS3
2
RDRS2
0
0
0
0
0
Figure 2-23. Port S Reduced Drive Register (RDRS)
Access: User read/write¹
1
0
RDRS1
RDRS0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
88
Freescale Semiconductor