|
MC9S12HY64 Datasheet, PDF (231/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
|
◁ |
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Figure 7-1. Block diagram of S12CPMU
Figure 7-2 shows a block diagram of the OSCLCP.
OSCCLK
Peak
Detector
Gain Control
VDDPLL = 1.8 V
EXTAL
VSSPLL
Rf
XTAL
Figure 7-2. OSCLCP Block Diagram
7.2 Signal Description
This section lists and describes the signals that connect off chip.
7.2.1 RESET
RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known
start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
7.2.2 EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is
the external clock input or the input to the crystal oscillator ampliï¬er. XTAL is the output of the crystal
oscillator ampliï¬er. The MCU internal OSCCLK is derived from the EXTAL input frequency. If OSCE=0,
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
231
|
▷ |