MC9S12HY64 Datasheet, PDF (47/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12HY/HA-Family
1.11 Resets and Interrupts
Consult the S12 CPU manual and the S12SINT section for information on exception processing.
1.11.1 Resets
Table 1-11. lists all Reset sources and the vector locations. Resets are explained in detail in the Section
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Vector Address
0xFFFE
0xFFFE
0xFFFE
0xFFFE
0xFFFC
0xFFFA
Table 1-11. Reset Sources and Vector Locations
Reset Source
CCR
Mask
Local Enable
Power-On Reset (POR)
Low Voltage Reset (LVR)
External pin RESET
Illegal Address Reset
Clock monitor reset
COP watchdog reset
None
None
None
None
None
None
None
None
None OSCE Bit in CPMUOSC register
None CR[2:0] in CPMUCOP register
1.11.2 Vectors
Table 1-12 lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Chapter 4, “Interrupt Module (S12SINTV1)) provides an interrupt vector base register (IVBR) to relocate
the vectors.
Table 1-12. Interrupt Vector Locations (Sheet 1 of 3)
Vector Address⁽¹⁾
Vector base + 0xF8
Vector base+ 0xF6
Vector base+ 0xF4
Vector base+ 0xF2
Vector base+ 0xF0
Vector base+ 0xEE
Vector base + 0xEC
Vector base+ 0xEA
Vector base+ 0xE8
Vector base+ 0xE6
Vector base + 0xE4
Vector base+ 0xE2
Interrupt Source
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real time interrupt
TIM0 timer channel 0
TIM0 timer channel 1
TIM0 timer channel 2
TIM0 timer channel 3
TIM0 timer channel 4
TIM0 timer channel 5
TIM0 timer channel 6
CCR
Mask
None
None
X Bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
Local Enable
None
None
IRQCR (XIRQEN)
IRQCR (IRQEN)
CPMUINT (RTIE)
TIM0TIE (C0I)
TIM0TIE (C1I)
TIM0TIE (C2I)
TIM0TIE (C3I)
TIM0TIE (C4I)
TIM0TIE (C5I)
TIM0TIE (C6I)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
47