MC9S12HY64 Datasheet, PDF (92/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12HYPIMV1)
1 _{Read: Anytime.}
Write: Anytime.
Field
7-0
PTP
Table 2-27. PTP Register Field Descriptions
Description
Port P general purpose input/output data—Data Register, LCD segment driver output, PWM channel output
Port P pins are associated with the PWM channel output and LCD segment driver output.
When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data
direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
• The LCD segment takes precedence over the PWM function and the general purpose I/O function is LCD
segment output is enabled
• The PWM function takes precedence over the general purpose I/O function if the PWM channel is enabled.
2.3.32 Port P Input Register (PTIP)
Address 0x0259
7
R PTIP7
6
PTIP6
5
PTIP5
4
PTIP4
3
PTIP3
2
PTIP2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-30. Port P Input Register (PTIP)
1 _{Read: Anytime.}
Write:Never, writes to this register have no effect.
Access: User read¹
1
PTIP1
0
PTIP0
u
u
Field
7-0
PTIP
Table 2-28. PTIP Register Field Descriptions
Description
Port P input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.33 Port P Data Direction Register (DDRP)
Address 0x025A
R
W
Reset
7
DDRP7
0
6
DDRP6
5
DDRP5
4
DDRP4
3
DDRP3
2
DDRP2
0
0
0
0
0
Figure 2-31. Port P Data Direction Register (DDRP)
Access: User read/write¹
1
0
DDRP1
DDRP0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
92
Freescale Semiconductor