MC9S12HY64 Datasheet, PDF (719/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Electrical Characteristics
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V_SS35 or V_DD35).
Table A-1. Absolute Maximum Ratings⁽¹⁾
Num
Rating
Symbol
Min
1 I/O, regulator and analog supply voltage
2 Voltage difference V_DDX to V_DDA
3 Voltage difference V_SSX to V_SSA
4 Voltage difference V_DDX to V_DDM1,2
5 Voltage difference V_SSX to V_SSM1,2
6 Voltage difference V_DDM1,2 to V_DDA
7 Voltage difference V_SSM1,2 to V_SSA
8 Digital I/O input voltage
9 EXTAL, XTAL
10 Instantaneous maximum current
Single pin limit for all digital I/O pins⁽²⁾
V_DD35
∆_VDDXA
∆_VSSXA
∆_VDDXM
∆_VSSXM
∆_VDDMA
∆_VSSMA
V_IN
V_ILV
I_D
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–25
11 Instantaneous maximum current
Single pin limit for all the power pins
I_DL
-50
12 Instantaneous maximum current
Single pin limit for EXTAL, XTAL
I_DL
–25
13 Storage temperature range
1. Beyond absolute maximum ratings device might be damaged.
Tstg
–65
2. All digital I/O pins are internally clamped to V_SSX and V_DDX, or V_SSA and V_DDA or V_SSM and V_DDM
Max
Unit
6.0
V
0.3
V
0.3
V
0.3
V
0.3
V
0.3
V
0.3
V
6.0
V
2.16
V
+25
mA
+50
mA
+25
mA
155
°C
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade
integrated circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
719