MC9S12HY64 Datasheet, PDF (147/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12P Memory Map Control (S12PMMCV1)
3.5.2 Chip Bus Control
The S12PMMC controls the address buses and the data buses that interface the bus masters (CPU12,
S12SBDM) with the rest of the system (master buses). In addition the MMC handles all CPU read data
bus swapping operations. All internal resources are connected to specific target buses (see Figure 3-12).
DBG
CPU
S12X0
BDM
S12X1
MMC “Crossbar Switch”
XBUS0
P-Flash
D-Flash
BDM
resources
SRAM
IPBI
Peripherals
Figure 3-12. S12P platform
3.5.2.1 Master Bus Prioritization regarding Access Conflicts on Target Buses
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
• CPU12 always has priority over BDM.
• BDM has priority over CPU12 when its access is stalled for more than 128 cycles. In the later case
the CPU will be stalled after finishing the current operation and the BDM will gain access to the
bus.
3.5.3 Interrupts
The MMC does not generate any interrupts
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
147