MC9S12HY64 Datasheet, PDF (412/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Pulse-Width Modulator (S12PWM8B8CV1)
Each channel counter can be read at anytime without affecting the count or the operation of the PWM
channel.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,
the immediate load of both duty and period registers with values from the buffers, and the output to change
according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a
channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the
PWMCNTx register. This allows the waveform to continue where it left off when the channel is
re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset
on the next selected clock.
NOTE
If the user wants to start a new “clean” PWM waveform without any
“history” from the old waveform, the user must write to channel counter
(PWMCNTx) prior to enabling the PWM channel (PWMEx = 1).
Generally, writes to the counter are done prior to enabling a channel in order to start from a known state.
However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is
similar to writing the counter when the channel is disabled, except that the new period is started
immediately with the output set according to the polarity bit.
NOTE
Writing to the counter while the channel is enabled can cause an irregular
PWM cycle to occur.
The counter is cleared at the end of the effective period (see Section 11.4.2.5, “Left Aligned Outputs” and
Section 11.4.2.6, “Center Aligned Outputs” for more details).
Table 11-10. PWM Timer Counter Conditions
Counter Clears ($00)
When PWMCNTx register written to
any value
Effective period ends
Counter Counts
When PWM channel is enabled
(PWMEx = 1). Counts from last value in
PWMCNTx.
Counter Stops
When PWM channel is disabled
(PWMEx = 0)
11.4.2.5 Left Aligned Outputs
The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are
selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the
corresponding PWM output will be left aligned.
In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two
registers, a duty register and a period register as shown in the block diagram in Figure 11-19. When the
PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to
also change state. A match between the PWM counter and the period register resets the counter and the
output flip-flop, as shown in Figure 11-19, as well as performing a load from the double buffer period and
duty register to the associated registers, as described in Section 11.4.2.3, “PWM Period and Duty”. The
counter counts from 0 to the value in the period register – 1.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
412
Freescale Semiconductor