MC9S12HY64 Datasheet, PDF (239/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.2.5 S12CPMU Interrupt Enable Register (CPMUINT)
This register enables S12CPMU interrupt requests.
0x0038
7
6
R
0
RTIE
W
5
4
3
0
0
LOCKIE
2
1
0
0
0
OSCIE
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-8. S12CPMU Interrupt Enable Register (CPMUINT)
Read: Anytime
Write: Anytime
Table 7-4. CRGINT Field Descriptions
Field
7
RTIE
4
LOCKIE
1
OSCIE
Description
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
PLL Lock Interrupt Enable Bit
0 PLL LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
Oscillator Corrupt Interrupt Enable Bit
0 Oscillator Corrupt interrupt requests are disabled.
1 Interrupt will be requested whenever OSCIF is set.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
239