MC9S12HY64 Datasheet, PDF (428/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Serial Communication Interface (S12SCIV5)
Table 12-4. SCICR1 Field Descriptions (continued)
Field
2
ILT
1
PE
0
PT
Description
Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The
counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the
stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
0 Idle character bit count begins after start bit
1 Idle character bit count begins after stop bit
Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the
most significant bit position.
0 Parity function disabled
1 Parity function enabled
Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even
parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an
odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.
0 Even parity
1 Odd parity
LOOPS
0
1
1
Table 12-5. Loop Functions
RSRC
x
0
1
Function
Normal operation
Loop mode with transmitter output internally connected to receiver input
Single-wire mode with TXD pin connected to receiver input
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
428
Freescale Semiconductor