MC9S12HY64 Datasheet, PDF (219/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12S Debug Module (S12SDBGV2)
Table 6-43. Breakpoint Mapping Summary
DBGBRK
0
1
X
1
1
BDM Bit
(DBGC1[4])
X
0
X
1
1
BDM
Enabled
X
X
1
0
1
BDM
Active
X
0
1
X
0
Breakpoint
Mapping
No Breakpoint
Breakpoint to SWI
No Breakpoint
Breakpoint to SWI
Breakpoint to BDM
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via
a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes
the BDM firmware code, checks the ENABLE and returns if ENABLE is not set. If not serviced by the
monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow.
If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code
could coincide with a DBG breakpoint. The CPU ensures that BDM requests have a higher priority than
SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid a repeated
breakpoint at the same address.
Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows
the BGND instruction is the first instruction executed when normal program execution resumes.
NOTE
When program control returns from a tagged breakpoint using an RTI or
BDM GO command without program counter modification it returns to the
instruction whose tag generated the breakpoint. To avoid a repeated
breakpoint at the same location reconfigure the DBG module in the SWI
routine, if configured for an SWI breakpoint, or over the BDM interface by
executing a TRACE command before the GO to increment the program flow
past the tagged instruction.
6.5 Application Information
6.5.1 State Machine scenarios
Defining the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2
respectively. SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only
in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR
register. Thus the existing encoding for SCRx[2:0] is not changed.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
219