MC9S12HY64 Datasheet, PDF (485/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Chapter 14
Timer Module (TIM16B8CV2) Block Description
Table 14-1. Revision History
Revision
Number
Revision Date
Sections
Affected
Description of Changes
V02.04
V02.05
V02.06
V02.07
1 Jul 2008
9 Jul 2009
26 Aug 2009
04 May 2010
14.3.2.12/14-50 - Revised flag clearing procedure, whereby TEN bit must be set when clearing
1
flags.
14.3.2.13/14-50
1
14.3.2.16/14-50
4
14.4.2/14-509
14.4.3/14-509
14.3.2.12/14-50 - Revised flag clearing procedure, whereby TEN or PAEN bit must be set
1
when clearing flags.
14.3.2.13/14-50 - Add fomula to describe prescaler
1
14.3.2.15/14-50
3
14.3.2.16/14-50
4
14.3.2.19/14-50
6
14.4.2/14-509
14.4.3/14-509
14.1.2/14-486 - Correct typo: TSCR ->TSCR1
14.3.2.15/14-50 - Correct reference: Figure 1-25 -> Figure 1-31
3
- Add description, “a counter overflow when TTOV[7] is set”, to be the
14.3.2.2/14-492 condition of channel 7 override event.
14.3.2.3/14-493 - Phrase the description of OC7M to make it more explicit
14.3.2.4/14-494
14.4.3/14-509
14.3.2.8/14-497 - Add Table 14-10
14.3.2.11/14-50 - in TCRE bit description part,add Note
0
- Add Figure 14-31
14.4.3/14-509
14.1 Introduction
The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable
prescaler.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
485