MC9S12HY64 Datasheet, PDF (293/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Analog-to-Digital Converter (ADC12B8CV1) Block Description
Table 8-11. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1
0
0
1
1
FRZ0
0
1
0
1
Behavior in Freeze Mode
Continue conversion
Reserved
Finish current conversion, then freeze
Freeze Immediately
8.3.2.5 ATD Control Register 4 (ATDCTL4)
Writes to this register will abort current conversion sequence.
Module Base + 0x0004
7
6
5
4
3
2
1
0
R
SMP2
W
SMP1
SMP0
PRS[4:0]
Reset
0
0
0
0
0
1
0
1
Figure 8-7. ATD Control Register 4 (ATDCTL4)
Read: Anytime
Write: Anytime
Table 8-12. ATDCTL4 Field Descriptions
Field
Description
7–5
SMP[2:0]
4–0
PRS[4:0]
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
Table 8-13 lists the available sample time lengths.
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
fATDCLK = _2-----×-----₍--f-P-B---R-U----S-S----+-----1-----₎
Refer to Device Specification for allowed frequency range of f_ATDCLK.
SMP2
0
0
0
0
1
1
1
Table 8-13. Sample Time Select
SMP1
0
0
1
1
0
0
1
SMP0
0
1
0
1
0
1
0
Sample Time
in Number of
ATD Clock Cycles
4
6
8
10
12
16
20
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
293