MC9S12HY64 Datasheet, PDF (313/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Register
Name
0x000F
CANTXERR
Bit 7
6
5
4
3
2
1
Bit 0
R TXERR7
W
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0x0010–0x0013 R
CANIDAR0–3 _W ^AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
0x0014–0x0017 R
CANIDMRx
W
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
0x0018–0x001B R
CANIDAR4–7 _W ^AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
0x001C–0x001F R
CANIDMR4–7 _W
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
0x0020–0x002F R
CANRXFG
W
See Section 9.3.3, “Programmer’s Model of Message Storage”
0x0030–0x003F R
CANTXFG
W
See Section 9.3.3, “Programmer’s Model of Message Storage”
= Unimplemented or Reserved
Figure 9-3. MSCAN Register Summary (continued)
9.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
9.3.2.1 MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
Module Base + 0x0000
R
W
Reset:
7
RXFRM
0
6
RXACT
5
CSWAI
4
SYNCH
3
TIME
2
WUPE
0
0
0
0
0
= Unimplemented
Figure 9-4. MSCAN Control Register 0 (CANCTL0)
Access: User read/write⁽¹⁾
1
0
SLPRQ
INITRQ
0
1
MC9S12HY/HA-Family Reference Manual Rev. 1.04
Freescale Semiconductor
313