MC9S12HY64 Datasheet, PDF (696/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Motor Controller (MC10B8CV1)
Offset Module Base + 0x0020 . . . 0x002F
Access: User read/write
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
S D8 D7 D6 D5 D4 D3 D2
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-9. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 1
Table 19-10. MCDCx Field Descriptions
Field
0
S
Description
SIGN — The SIGN bit is used to define which output will drive the PWM signal in (dual) full-H-bridge modes. The
SIGN bit has no effect in half-bridge modes. See Section 19.4.1.3.2, “Sign Bit (S)”, and table Table 19-12 for
detailed information about the impact of RECIRC and SIGN bit on the PWM output.
Whenever FAST = 1, the bits D10, D9, D1, and D0 will be set to 0 if the duty cycle register is written.
For example setting MCDCx = 0x0158 with FAST = 0 gives the same output waveform as setting
MCDCx = 0x5600 with FAST = 1 (with FAST = 1, the low byte of MCDCx needs not to be written).
The state of the FAST bit has impact only during write and read operations. A change of the FAST bit (set
or clear) without writing a new value does not impact the internal interpretation of the duty cycle values.
To prevent the output from inconsistent signals, the duty cycle registers are double buffered. The motor
controller module will use working registers to generate the output signals. The working registers are
copied from the bus accessible registers at the following conditions:
• MCPER is set to 0 (all channels are disabled in this case)
• MCAM[1:0] of the respective channel is set to 0 (channel is disabled)
• A PWM timer counter overflow occurs while in half H-bridge or full H-bridge mode
• A PWM channel pair is configured to work in Dual Full H-Bridge mode and a PWM timer counter
overflow occurs after the odd¹ duty cycle register of the channel pair has been written.
In this way, the output of the PWM will always be either the old PWM waveform or the new PWM
waveform, not some variation in between.
Reads of this register return the most recent value written. Reads do not necessarily return the value of the
currently active sign, duty cycle, and dither functionality due to the double buffering scheme.
1. Odd duty cycle register: MCDCx+1, x = 2⋅n
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
696
Freescale Semiconductor