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MC9S12HY64 Datasheet, PDF (737/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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A.3.1.13 Set Field Margin Level (FCMD=0x0E)
The maximum set ï¬eld margin level time is given by:
t
=
350
â
----------1-----------
f NVMBUS
Electrical Characteristics
A.3.1.14 Erase Verify D-Flash Section (FCMD=0x10)
The time required to Erase Verify D-Flash for a given number of words NW is given by:
tdcheck â (450 + NW) â
f---N----V---M1----B---U----S
A.3.1.15 Program D-Flash (FCMD=0x11)
D-Flash programming time is dependent on the number of words being programmed and their location
with respect to a row boundary since programming across a row boundary requires extra steps. The D-
Flash programming time is speciï¬ed for different cases: 1,2,3,4 words and 4 words across a row boundary.
The typical D-Flash programming time is given by the following equation, where NW denotes the number
of words; BC=0 if no row boundary is crossed and BC=1 if a row boundary is crossed:
tdpgm
â
ï£ï£« ( 14
+
( 54
â
NW)
+
(14
â
BC) )
â
---------1---------
f NVMOP


+
ï£ï£« ( 500
+
( 525
â
NW)
+
( 100
â
BC))
â
----------1-----------
f NVMBUS


The maximum D-Flash programming time is given by:
tdpgm
â

ï£
(
14
+
( 54
â
NW)
+
( 14
â
BC) )
â
f---N----V--1-M----O----P


+

ï£
(
500
+
( 750
â
NW )
+
( 100
â
BC))
â
f---N----V---M1----B---U----S


A.3.1.16 Erase D-Flash Sector (FCMD=0x12)
Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given
by:
tdera
â
5025
â
-f--N----V--1-M----O----P
+
700
â
----------1-----------
f NVMBUS
Maximum D-Flash sector erase times is given by:
tdera â 20100 â
-f--N----V--1-M----O----P + 3400 â
f---N----V---M1----B---U----S
The D-Flash sector erase time is ~5ms on a new device and can extend to ~20ms as the ï¬ash is cycled.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
737
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