MC9S12HY64 Datasheet, PDF (264/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.2.22 S12CPMU Protection Register (CPMUPROT)
This register protects the clock configuration registers from accidental overwrite:
CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L and CPMUOSC
0x02FB
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-29. S12CPMU Protection Register (CPMUPROT)
0
PROT
0
Field
0
PROT
Description
Clock Configuration Registers Protection Bit — This bit protects the clock configuration registers from
accidental overwrite (see list of affected registers above).
Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit.
0 Protection of clock configuration registers is disabled.
1 Protection of clock configuration registers is enabled. CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL,
CPMUIRCTRIMH/L and CPMUOSC registers are not writable.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
264
Freescale Semiconductor