MC9S12HY64 Datasheet, PDF (508/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Timer Module (TIM16B8CV2) Block Description
Bus Clock
PR[2:1:0]
PRESCALER
PACLK
PACLK/256
PACLK/65536
CLK[1:0]
MUX
channel 7 output
compare
TCRE
TCNT(hi):TCNT(lo)
16-BIT COUNTER
CHANNEL 0
16-BIT COMPARATOR
TC0
EDG0A EDG0B
CHANNEL 1
16-BIT COMPARATOR
TC1
EDG1A EDG1B
CHANNEL2
CLEAR COUNTER
TE
C0F
EDGE
DETECT
OM:OL0
TOV0
C1F
EDGE
DETECT
OM:OL1
TOV1
CxI
CxF
TOF
TOI
INTERRUPT
LOGIC
TOF
C0F
IOC0
C1F
IOC1
CH. 0 CAPTURE
IOC0 PIN
LOGIC _{CH. 0COMPARE}
IOC0 PIN
CH. 1 CAPTURE
IOC1 PIN
LOGIC _{CH. 1 COMPARE}
IOC1 PIN
CHANNEL7
16-BIT COMPARATOR
TC7
EDG7A
EDG7B
C7F
EDGE
DETECT
OM:OL7
TOV7
C7F
IOC7
PAOVF
PACNT(hi):PACNT(lo)
PACLK/65536
PACLK/256
16-BIT COUNTER
PACLK
INTERRUPT
REQUEST
INTERRUPT
LOGIC
PAOVI
PAOVF
PAI
PAIF
PEDGE
PAE
TEN
DIVIDE-BY-64
CH.7 CAPTURE
IOC7 PIN ^{PA INPUT}
LOGIC
IOC7 PIN
CH. 7 COMPARE
EDGE
DETECT
PAIF
Bus Clock
PAOVF
PAOVI
Figure 14-30. Detailed Timer Block Diagram
14.4.1 Prescaler
The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
508
Freescale Semiconductor