MC9S12HY64 Datasheet, PDF (623/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

64 KByte Flash Module (S12FTMRC64K1V1)
Table 17-6. FCLKDIV Field Descriptions (continued)
Field
Description
6
FDIVLCK
5–0
FDIV[5:0]
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
restore writability to the FDIV field.
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms. Table 17-7 shows recommended values for FDIV[5:0] based on the
BUSCLK frequency. Please refer to Section 17.4.3, “Flash Command Operations,” for more information.
Table 17-7. FDIV values for various BUSCLK Frequencies
BUSCLK Frequency
(MHz)
MIN¹
MAX²
FDIV[5:0]
BUSCLK Frequency
(MHz)
MIN¹
MAX²
1.0
1.6
0x00
16.6
17.6
1.6
2.6
0x01
17.6
18.6
2.6
3.6
0x02
18.6
19.6
3.6
4.6
0x03
19.6
20.6
4.6
5.6
0x04
20.6
21.6
5.6
6.6
0x05
21.6
22.6
6.6
7.6
0x06
22.6
23.6
7.6
8.6
0x07
23.6
24.6
8.6
9.6
0x08
24.6
25.6
9.6
10.6
0x09
25.6
26.6
10.6
11.6
0x0A
26.6
27.6
11.6
12.6
0x0B
27.6
28.6
12.6
13.6
0x0C
28.6
29.6
13.6
14.6
0x0D
29.6
30.6
14.6
15.6
0x0E
30.6
31.6
15.6
16.6
0x0F
31.6
32.6
1 _{BUSCLK is Greater Than this value.}
2 _{BUSCLK is Less Than or Equal to this value.}
FDIV[5:0]
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
17.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
623