MC9S12HY64 Datasheet, PDF (163/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Background Debug Module (S12SBDMV1)
5.3.2 Register Descriptions
A summary of the registers associated with the BDM is shown in Figure 5-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Global Register
Address Name
Bit 7
6
5
0x3_FF00 Reserved R X
X
X
W
0x3_FF01 BDMSTS R
BDMACT
0
ENBDM
W
0x3_FF02 Reserved R X
X
X
W
0x3_FF03 Reserved R X
X
X
W
0x3_FF04 Reserved R X
X
X
W
0x3_FF05 Reserved R X
X
X
W
0x3_FF06 BDMCCR R
CCR7
W
CCR6
CCR5
0x3_FF07 Reserved R
0
0
0
W
0x3_FF08 BDMPPR R
0
0
BPAE
W
0x3_FF09 Reserved R
0
0
0
W
0x3_FF0A Reserved R
0
0
0
W
0x3_FF0B Reserved R
0
0
0
W
4
3
2
1
Bit 0
X
X
X
0
0
SDV
TRACE
0
UNSEC
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CCR4
CCR3
CCR2
CCR1
CCR0
0
0
0
0
0
0
BPP3
BPP2
BPP1
BPP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented, Reserved
X
= Indeterminate
0
Figure 5-2. BDM Register Summary
= Implemented (do not alter)
= Always read zero
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
163