MC9S12HY64 Datasheet, PDF (381/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Inter-Integrated Circuit (IICV3) Block Description
10.4.1.11 General Call Address
To broadcast using a general call, a device must first generate the general call address($00), then after
receiving acknowledge, it must transmit data.
In communication, as a slave device, provided the GCEN is asserted, a device acknowledges the broadcast
and receives data until the GCEN is disabled or the master device releases the bus or generates a new
transfer. In the broadcast, slaves always act as receivers. In general call, IAAS is also used to indicate the
address match.
In order to distinguish whether the address match is the normal address match or the general call address
match, IBDR should be read after the address byte has been received. If the data is $00, the match is
general call address match. The meaning of the general call address is always specified in the first data byte
and must be dealt with by S/W, the IIC hardware does not decode and process the first data byte.
When one byte transfer is done, the received data can be read from IBDR. The user can control the
procedure by enabling or disabling GCEN.
10.4.2 Operation in Run Mode
This is the basic mode of operation.
10.4.3 Operation in Wait Mode
IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate
normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module
enters a power conservation state during wait mode. In the later case, any transmission or reception in
progress stops at wait mode entry.
10.4.4 Operation in Stop Mode
The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC
register states.
10.5 Resets
The reset state of each individual bit is listed in Section 10.3, “Memory Map and Register Definition,”
which details the registers and their bit-fields.
10.6 Interrupts
IICV3 uses only one interrupt vector.
Table 10-11. Interrupt Summary
Interrupt Offset Vector Priority
Source
Description
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
381