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MC9S12HY64 Datasheet, PDF (572/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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48 KByte Flash Module (S12FTMRC48K1V1)
Address
& Name
7
6
5
4
3
2
1
0
0x0012
R
0
0
0
0
0
0
0
0
FRSV6 W
0x0013
R
0
0
0
0
0
0
0
0
FRSV7 W
= Unimplemented or Reserved
Figure 16-4. FTMRC48K1 Register Summary (continued)
16.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R FDIVLD
W
FDIVLCK
FDIV[5:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV ï¬eld.
CAUTION
The FCLKDIV register must never be written to while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
Table 16-6. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6
FDIVLCK
5â0
FDIV[5:0]
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
Clock Divider Locked
0 FDIV ï¬eld is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
restore writability to the FDIV ï¬eld.
Clock Divider Bits â FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms. Table 16-7 shows recommended values for FDIV[5:0] based on the
BUSCLK frequency. Please refer to Section 16.4.3, âFlash Command Operations,â for more information.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
572
Freescale Semiconductor
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