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MC9S12HY64 Datasheet, PDF (246/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.2.9 S12CPMU COP Control Register (CPMUCOP)
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL=1 and PCE=1 the COP
continues to run, else the COP counter halts in Stop Mode.
0x003C
7
6
5
4
R
0
0
WCOP
RSBCK
W
WRTMASK
3
2
1
0
0
CR2
CR1
CR0
Reset
F
0
0
0
0
F
F
F
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
details.
= Unimplemented or Reserved
Figure 7-12. S12CPMU COP Control Register (CPMUCOP)
Read: Anytime
Write:
1. RSBCK: anytime in special mode; write to â1â but not to â0â in normal mode
2. WCOP, CR2, CR1, CR0:
â Anytime in special mode, when WRTMASK is 0, otherwise it has no effect
â Write once in normal mode, when WRTMASK is 0, otherwise it has no effect.
â Writing CR[2:0] to â000â has no effect, but counts for the âwrite onceâ condition.
â Writing WCOP to â0â has no effect, but counts for the âwrite onceâ condition.
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL bit (writing a different value or loosing UPOSC status) re-starts the COP
time-out period.
In normal mode the COP time-out period is restarted if either of these conditions is true:
1. Writing a non-zero value to CR[2:0] (anytime in special mode, once in normal mode) with
WRTMASK = 0.
2. Writing WCOP bit (anytime in special mode, once in normal mode) with WRTMASK = 0.
3. Changing RSBCK bit from â0â to â1â.
In special mode, any write access to CPMUCOP register restarts the COP time-out period.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
246
Freescale Semiconductor
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