MC9S12HY64 Datasheet, PDF (77/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12HYPIMV1)
2.3.10 ECLK Control Register (ECLKCTL)
Address 0x001C (PRR)
R
W
Reset:
7
NECLK
1
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
DIV16
EDIV4
EDIV3
EDIV2
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-8. ECLK Control Register (ECLKCTL)
Access: User read/write¹
1
0
EDIV1
EDIV0
0
0
Table 2-10. ECLKCTL Register Field Descriptions
Field
Description
7
NECLK
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate of equivalent to
the internal bus clock.
5
DIV16
1 ECLK disabled
0 ECLK enabled
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
4-0
EDIV
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3,...
11111 ECLK rate = bus clock rate divided by 32
2.3.11 PIM Reserved Register
Address 0x001D (PRR)
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-9. PIM Reserved Register
Access: User read¹
1
0
0
0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
77