MC9S12HY64 Datasheet, PDF (185/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

— Begin and End alignment of tracing to trigger
S12S Debug Module (S12SDBGV2)
6.1.4 Modes of Operation
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When
the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already
armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
Table 6-2. Mode Dependent Restriction Summary
BDM
Enable
x
0
0
1
1
BDM
Active
x
0
1
0
1
MCU
Secure
1
0
0
0
0
Comparator
Matches Enabled
Yes
Yes
Yes
No
Breakpoints
Possible
Tagging
Possible
Yes
Yes
Only SWI
Yes
Active BDM not possible when not enabled
Yes
Yes
No
No
Tracing
Possible
No
Yes
Yes
No
6.1.5 Block Diagram
TAGHITS
SECURE
CPU BUS
COMPARATOR A
COMPARATOR B
COMPARATOR C
MATCH0
MATCH1
MATCH2
TAGS
BREAKPOINT REQUESTS
TO CPU
TRANSITION
TAG &
MATCH
CONTROL
LOGIC
STATE
STATE
STATE SEQUENCER
TRACE
CONTROL
TRIGGER
READ TRACE DATA (DBG READ DATA BUS)
Figure 6-1. Debug Module Block Diagram
6.2 External Signal Description
There are no external signals associated with this module.
TRACE BUFFER
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
185