MC9S12HY64 Datasheet, PDF (50/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12HY/HA-Family
1.11.3.4 Memory
The RAM arrays are not initialized out of reset.
1.12 COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are
loaded from the Flash register FOPT. See Table 1-13 and Table 1-14 for coding. The FOPT register is
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence.
Table 1-13. Initial COP Rate Configuration
NV[2:0] in
FOPT Register
000
001
010
011
100
101
110
111
CR[2:0] in
COPCTL Register
111
110
101
100
011
010
001
000
Table 1-14. Initial WCOP Configuration
NV[3] in
FOPT Register
1
0
WCOP in
COPCTL Register
0
1
1.13 ATD External Trigger Input Connection
The ATD module includes external trigger inputs ETRIG[3:0]. The external trigger allows the user to
synchronize ATD conversion to external trigger events. Table 1-15 shows the connection of the external
trigger inputs.
Table 1-15. ATD External Trigger Sources
External Trigger
Input
Connectivity
ETRIG0
PP1⁽¹⁾
ETRIG1
PP3¹
ETRIG2
TIM0 Channel output 2⁽²⁾
ETRIG3
TIM0 Channel output 3²
1. When LCD segment output driver is enabled on PP1/PP3, the ATD
external trigger function will be unavailable
2. Independent of the TIM0OCPD3/2 bit setting
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
50
Freescale Semiconductor