MC9S12HY64 Datasheet, PDF (674/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Liquid Crystal Display (LCD40F4BV1) Block Description
Table 18-8. LCD Clock and Frame Frequency
Source clock
Frequency in
MHz
IRCCLK = 16.0
LCD Clock Prescaler
LCLK2 LCLK1 LCLK0
1
1
0
1
1
1
Divider
LCD Clock
Frequency [Hz]
Frame Frequency [Hz]
1/1 Duty 1/2 Duty 1/3 Duty 1/4 Duty
65536
244
131072
122
244
122
81
61
122
61
40
31
For other combinations of IRCCLK and divider not shown in Table 18-8, the following formula may be
used to calculate the LCD frame frequency for each multiplex mode:
LCD Frame Frequency (Hz) = ⁽---^I--^R----^C--_D--^C--_i--^Lv---_i-^K-_d---_e-⁽-_r-^H-----^z--⁾---⁾ ⋅ Duty
The possible divider values are shown in Table 18-8.
18.4.1.3 LCD RAM
For a segment on the LCD to be displayed, data must be written to the LCD RAM which is shown in
Section 18.3, “Memory Map and Register Definition”. The 160 bits in the LCD RAM correspond to the
160 segments that are driven by the frontplane and backplane drivers. Writing a 1 to a given location will
result in the corresponding display segment being driven with a differential RMS voltage necessary to turn
the segment ON when the LCDEN bit is set and the corresponding FP[39:0]EN bit is set. Writing a 0 to a
given location will result in the corresponding display segment being driven with a differential RMS
voltage necessary to turn the segment OFF. The LCD RAM is a dual port RAM that interfaces with the
internal address and data buses of the MCU. It is possible to read from LCD RAM locations for scrolling
purposes. When LCDEN = 0, the LCD RAM can be used as on-chip RAM. Writing or reading of the
LCDEN bit does not change the contents of the LCD RAM. After a reset, the LCD RAM contents will be
indeterminate.
18.4.1.4 LCD Driver System Enable and Frontplane Enable Sequencing
If LCDEN = 0 (LCD40F4BV1 driver system disabled) and the frontplane enable bit, FP[39:0]EN, is set,
the frontplane driver waveform will not appear on the output until LCDEN is set. If LCDEN = 1
(LCD40F4BV1 driver system enabled), the frontplane driver waveform will appear on the output as soon
as the corresponding frontplane enable bit, FP[39:0]EN, in the registers FPENR0–FPENR4 is set.
18.4.1.5 LCD Bias and Modes of Operation
The LCD40F4BV1 driver has five modes of operation:
• 1/1 duty (1 backplane), 1/1 bias (2 voltage levels)
• 1/2 duty (2 backplanes), 1/2 bias (3 voltage levels)
• 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels)
• 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels)
• 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
674
Freescale Semiconductor