MC9S12HY64 Datasheet, PDF (275/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

7.5 Resets
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.5.1 General
All reset sources are listed in Table 7-25. Refer to MCU specification for related vector addresses and
priorities.
Table 7-25. Reset Summary
Reset Source
Power-On Reset (POR)
Low Voltage Reset (LVR)
External pin RESET
Illegal Address Reset
Clock Monitor Reset
COP Reset
Local Enable
None
None
None
None
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
7.5.2 Description of Reset Operation
Upon detection of any reset of Table 7-25, an internal circuit drives the RESET pin low for 512 PLLCLK
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU waits
for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source.
Table 7-26 shows which vector will be fetched.
Table 7-26. Reset Vector Selection
Sampled RESET Pin
(256 cycles after
release)
1
Oscillator monitor
fail pending
0
COP
time out
pending
0
1
1
X
1
0
1
0
X
X
Vector Fetch
POR
LVR
Illegal Address Reset
External pin RESET
Clock Monitor Reset
COP Reset
POR
LVR
Illegal Address Reset
External pin RESET
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
f_VCORST.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
275